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cystech electronics corp. spec. no. : c554qp issued date : 2010.11.17 revised date : page no. : 1/12 em5103 cystek product specification 3a low dropout ldo em5103 general description em5103 is a 3a low dropout linear regulator designed for low dropout and high current applications. this device works with dual supplies, a control in put for the control circuitry and a power input as low as 1.2v for providing current to output. it features 3a output current and ultra-low-drop output voltage as well as full protection functions. v out can be as low as 0.8v. features v in range 1.2v to 5.5v 300mv @ 3a dropout voltage v out is adjustable (0.8v min) otp and ocp functions excellent line regulation very low on-resistance excellent load regulation enable & power good signal 3a guaranteed output current* *check thermal design information. applications notebook & netbook chipset supplies graphic cards & mb server system low voltage logic supplies smps post regulators ordering information part number package em5103qp psop-8 (pb-free lead plating package) EM5103NA dfn33-10l (pb-free lead plating package) pin configuration psop-8 dfn3 3-10l
cystech electronics corp. spec. no. : c554qp issued date : 2010.11.17 revised date : page no. : 2/12 em5103 cystek product specification typical application circuit psop-8 dfn3 3-10l pin assignment pin no. pin name psop-8 dfn3 3-10l pin function pok 1 5 power ok indication. pok is an open-drain output. an external pull high resistor connected to this pin is required. en 2 6 enable input. pulling the pin below 0.4v turns the regulator off. vin 3 7,8,9 input voltage. this is the drain input to the power device that supplies current to the output pin. v in cannot be forced higher than v cntl. cntl 4 10 supply input for control circuit. cntl provides supply voltage to the control circuitry and driver for the pass transistor. the driving capability of output current is proportioned to the v cntl . for the device to regulate, the voltage on this pin must be at least 2.0v greater than the output voltage, and no less than v cntl_min . nc 5 - no connection inside chip. vout 6 1,2,3 output voltage. v out is power output pin. an internal pull low resistance exists when the device is disabled. minimum 22 f low esr ceramic holding capacitor is required at this pin for stabilizing v out voltage. fb 7 4 feedback voltage. fb is the inverting input to the error amplifier. a resistor divider from the output to gnd is used to set the regulation voltage as v out = (1 + r 1 /r 2 ) 0.8v (v). this pin has high impedance and should be kept from noisy source to guarantee stable operation. gnd 8 11 ground.
cystech electronics corp. spec. no. : c554qp issued date : 2010.11.17 revised date : page no. : 3/12 em5103 cystek product specification function block diagram absolute maximum ratings (note 1) v in ---------------- ------------------ ---------------------------------- ------------------ -------- -0.3v to +6.0v v cntl (note 1) ------------------ ------------------------------------------------------------ ----- -0.3v to +6.0v other pins-------------- ------------------------------------ ----------------- --------- -0.3v to (v cntl +0.3v) package thermal resistance, ja , psop-8 (note 2) ---------------- ------------------ --------- 75c c/w dfn3 j 3-10l ---------------------------------- --------- 60 c c/w package thermal resistance, jc , psop-8 (note 2) ---------------- ------------------ --------- 15c c/w power dissipation, p d @ t a = 25c c, psop-8 (note 3) -------------- --------------- --------------- 1.9w dfn3 j 3-10l --------- ------------------------------ ---- 1.67w junction temperature----- ------------------------------------------------------------ --------------- 150 c c lead temperature (soldering, 10 sec.)------------ ------------------------------ ------------------ 260 c c storage temperature ------------ --------------- -------------------------------------------- -65 c c to 150 c c esd susceptibility (note4) hbm (human body mode)----------- ------------------ ----------------- --------------- ------------ 2kv mm (machine mode)----- --------------------------------------------------------------------------- - 200v recommended operating conditions (note5) supply input voltage, v in ------------------ --------------------------------------------- ----- 1.0v to v cntl control voltage, v cntl --------------- ------------------------------------ ----------------- ---- 3.0v to 5.5v junction temperature -------- ------------------------------------------------ ------------- ?-- ? 40c c to 125 c c ambient temperature ------ ----------------- --------------------------------------------- ----- ? ? 40c c to 85 c c
cystech electronics corp. spec. no. : c554qp issued date : 2010.11.17 revised date : page no. : 4/12 em5103 cystek product specification electrical characteristics @ v cntl =5v, t a =25 , unless otherwise specified parameter symbol test conditions min typ max units supply input section control input voltage v cntl v out = v ref 3.0 - 5.5 v por threshold v cntlrth - 2.7 - v por hysteresis v cntlhys - 0.2 - v power input voltage v in v out =v ref 1.0 - v cntl v control input current in i cntl_sd v in =v cntl =5v, i out =0a,v en =0v - 10 30 a quiescent current i q v in =v cntl =v en =5v, i out =0a, v out =v ref - 0.9 1.5 ma feedback reference voltage v ref v in =v cntl =v en =5v, i out =0a, v out =v ref 0.788 0.8 0.812 v feedback input current i fb - 5 - na v in line regulation v ref(line) 1.2v90% to pok rising 0.5 1.0 2.0 ms over current protection ocp threshold level i ocp v in =v cntl =v en =5v, v out =v ref 3.2 4.0 - a output short circuit current i sc v in =v cntl =v en =5v, v out =0v 1.5 2.5 - a
cystech electronics corp. spec. no. : c554qp issued date : 2010.11.17 revised date : page no. : 5/12 em5103 cystek product specification parameter symbol test conditions min typ max units thermal protection thermal shutdown temperature t sd v in =v cntl =v en =5v, i out =0a, v out =v ref - 160 - ?c thermal shutdown hysteresis t sdhys v in =v cntl =v en =5v, i out =0a, v out =v ref - 30 - c? note 1. stresses listed as the above ?absolute maximum ratings? may cause permanent damage to the device. these are for stress ratings. functional operation of the device at thes e or any other conditions bey ond those indicated in the operational sections of the specificati ons is not implied. exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. note 2. ja is measured in the natural convection at t a =25 c on a 4-layers high effective thermal conductivity test board with minimum copper area of jedec 51-7 thermal measurement standard. the case point of jc is on the expose pad for psop-8 package. note 3. ja is 52 c/w for psop-8 packages on jedec 51-7 (4 la yers,2s2p) thermal test board with 50mm 2 copper area. note 4. devices are esd sensitive. handling precaution is recommended. note 5. the device is not guaranteed to function outside its operating conditions. note 6. load regulation is measured by a current pulse with 50hz frequency and 10% duty cycle. note 7. the dropout voltage is defined as (v in -v out ), which is measured when v out equal to (v out,(normal) -100mv).
cystech electronics corp. spec. no. : c554qp issued date : 2010.11.17 revised date : page no. : 6/12 em5103 cystek product specification typical operating characteristics power on from v cntl power on from v in v cntl =5v, v in = 3.3v, c out = 1000 f, no load. v cntl =5v, v in = 3.3v, c out = 1000 f, no load. turn on from en v cntl v out dropout voltage vs output current v cntl =5v, v in = 3.3v, c ou t = 1000 f, no load. v cnt l =5v v out =1. 6 v output short circuit output voltage vs output current v in =v cnt l =5v v ou t =v ref v cnt l = v in = 5v, v out =1.0v p ok i in v in v out p ok i in v en p ok i in v out o u t p u t v o l t a g e ( v ) output current(a) 0a 1a 2a 3a 4a 5a 0. 8v 0. 6v 0. 4v 0. 2v 0v
cystech electronics corp. spec. no. : c554qp issued date : 2010.11.17 revised date : page no. : 7/12 em5103 cystek product specification typical operating characteristics(cont.) load transient response quiescent current vs input voltage v out = v ref v cntl = 5v, v in =3.3v, c out = 22 f q uiesc ent c urren t v s . temperature fb voltag e v s . tempera t ure line regula t ion shutdo w n curren t v s . in put voltag e v in =v cntl (v) i out v out
cystech electronics corp. spec. no. : c554qp issued date : 2010.11.17 revised date : page no. : 8/12 em5103 cystek product specification typical operating characteristics(cont.) o n resistance vs. temperature v cntl =5v v out =1.6v. functional description enable function em5103 is enabled if the voltage of the en pin is greater than 1.4v. if the voltage of the en pin is less than 0.4v, the ic will be disabled. the quiescent current can be decreased to be less than 10 a typically. por ? power on reset to let em5103 start to operation, cntl voltage must be high er than its por voltage even when en voltage is pulled higher than enable high voltage. typical por voltage is 2.7v. vout voltage adjustment the v out voltage of em5103 can be adjusted by external volta ge divider. refer to typical application circuit, v out voltage is calculated by the following equation:
cystech electronics corp. spec. no. : c554qp issued date : 2010.11.17 revised date : page no. : 9/12 em5103 cystek product specification over current limit function em5103 features over current limiting function as well as output short circuit current fold back function. typically, before the thermal protection is triggered, em5103 can lim it its output current to 4.0a. when output voltage is decreased, the limiting current level also decreases. when v out is short to gnd, or v out voltage is zero, the output current level is limited to 2.5a, typically. input and output capacitor selection for cntl pin, a 1 f ceramic capacitor is enough for byp assing the supply of cntl to gnd. for v in pin, 10 f or larger ceramic capacitor is required to provide bypass path in transient current demand. v out pin is also recommended to have 22 f or larger ceramic capacitor to be stable and reduce the v out voltage dip when fast loading transient is happened. a feed-forward capacitor can be placed between v out and fb pin to speed up the transient response, optionally. power dissipation the max power depends on some conditions, including thermal impedance, pcb layout, airflow, and so on. the max power dissipation can be calculated by the formula as below: p d(max) =(t j(max) -t a ) / ja t j(max) is the max junction temperature; ja is the thermal impedance from junction to ambient. the thermal impedance ja of exposed sop-8 is package design and pcb design dependent. the thermal impedance can be reduced by increasing the copper area under the exposed pad of the sop-8 package. so, to let the copper area as large as possible is helpful for the thermal performance of the exposed sop-8 package. for recommended specification of em5103, the max junction temperature is 125 degree c. the ja of exposed sop-8 is 75c/w on the standard jedec 51-7(4 layers, 2s2p , copper 2 oz) thermal test board. the max power dissipation (at 25c ambient, on the min exposed pad layout) can be calculated as below: p d (max at 25c) =(125c ? 25c) / (75c/w) = 1.33w
cystech electronics corp. spec. no. : c554qp issued date : 2010.11.17 revised date : page no. : 10/12 em5103 cystek product specification recommended wave soldering condition soldering time product peak temperature pb-free devices 5 +1/-1 seconds 260 +0/-5 c recommended temperature profile for ir reflow pb-free assembly profile feature sn-pb eutectic assembly average ramp-up rate 3 c/second max. 3 c/second max. (tsmax to tp) preheat 100 c 150 c ? temperature min(t s min) ? temperature max(t s max) 150 c 200 c ? time(ts min to ts max ) 60-120 seconds 60-180 seconds time maintained above: ? temperature (t l ) 183 c 217 c ? time (t l ) 60-150 seconds 60-150 seconds peak temperature(t p ) 240 +0/-5 c 260 +0/-5 c time within 5 c of actual peak 10-30 seconds 20-40 seconds temperature(tp) ramp down rate 6 c/second max. 6 c/second max. 6 minutes max. 8 minutes max. time 25 c to peak temperature note : all temperatures refer to topside of t he package, measured on the package body surface.
cystech electronics corp. spec. no. : c554qp issued date : 2010.11.17 revised date : page no. : 11/12 em5103 cystek product specification psop-8 dimension marking: device name 8-lead psop-8 plastic surface mounted package cystek package code: qp date code *:typical inches millimeters inches millimeters dim min. max. min. max. dim min. max. min. max. a 0.1850 0.2008 4.70 5.10 h 0.0157 0.0327 0.40 0.83 b 0.1457 0.1614 3.70 4.10 i 0.0075 0.0102 0.19 0.26 c 0.2283 0.2441 5.80 6.20 j 0.0098 0.0197 0.25 0.50 d 0.0130 0.0200 0 8 0 8 0.33 0.51 k e 0.05* 1.27 * m 0.0764 0.0980 1.94 2.49 f 0.0472 0.0638 1.20 1.62 n 0.0764 0.0980 1.94 2.49 g 0.0032 0.0110 0.08 0.28 notes : 1.controlling dimension : millimeters. 2.maximum lead thickness includes lead finish thickness, and minimum lead thickness is the minimum thickness of base material. 3.if there is any question with packing specification or packing method, please c ontact your local cystek sales office. material : ? mold compound : epoxy resin family, flammability solid burning class:ul94v-0
cystech electronics corp. spec. no. : c554qp issued date : 2010.11.17 revised date : page no. : 12/12 em5103 cystek product specification dfn3 3-10l dimension *:typical inches marking: device name 10-lead dfn3 3-10l plastic surface mounted package cystek package code: na date code millimeters inches millimeters dim min. max. min. max. dim min. max. min. max. a 0.028 0.031 0.70 0.80 d2 0.087 0.106 2.20 2.70 a1 0.000 0.020 0.00 0.50 e2 0.055 0.069 1.40 1.75 a3 0.008* 0.20* e 0.020* 0.50* b 0.007 0.012 0.18 0.30 l 0.012 0.020 0.30 0.50 d 0.118* 3.0* k 0.008 - 0.20 - e 0.118* 3.0* notes : 1.controlling dimension : millimeters. 2.maximum lead thickness includes lead finish thickness, and minimum lead thickness is the minimum thickness of base material. 3.if there is any question with packing specification or packing method, please c ontact your local cystek sales office. material : ? mold compound : epoxy resin family, flammability solid burning class:ul94v-0 important notice: ? all rights are reserved. reproduction in whole or in part is prohibited without the prior written approval of cystek. ? cystek reserves the right to make changes to its products without notice. ? cystek semiconductor products are not warranted to be suitable for use in life-support applications, or systems. ? cystek assumes no liability for any consequence of customer pr oduct design, infringement of pat ents, or application assistance .

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